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    -- Company:
    -- Engineer:
    --
    -- Create Date: 11:03:26 11/21/2016
    -- Design Name:
    -- Module Name: Main - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    use IEEE.NUMERIC_STD.ALL;

    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity Main is
    PORT (
    clk : in std_logic;
    din : in std_logic_vector(3 downto 0) := (others => '0');
    reset : in std_logic := '1';
    start : in std_logic := '0';
    C: out std_logic := '0';
    display: out STD_LOGIC_VECTOR (6 downto 0)
    );
    end Main;


    architecture Behavioral of Main is
    COMPONENT Rom_asyn
    PORT(
    addr : IN std_logic_vector(3 downto 0);
    data : OUT std_logic_vector(7 downto 0)
    );
    END COMPONENT;

    COMPONENT db_fsm
    PORT( button : IN STD_LOGIC;
    result : OUT STD_LOGIC;
    clk : IN STD_LOGIC);
    END COMPONENT;

    COMPONENT displayModule
    PORT(
    clk : IN std_logic;
    reset : IN std_logic;
    val1 : IN std_logic_vector(3 downto 0);
    val2 : IN std_logic_vector(3 downto 0);
    C : OUT std_logic;
    display : OUT std_logic_vector(6 downto 0)
    );
    END COMPONENT;

    COMPONENT BaudRate
    PORT(
    clk : IN std_logic;
    reset : IN std_logic;
    baud : OUT std_logic
    );
    END COMPONENT;

    signal clk_slow : std_logic := '0';
    signal start_ok : std_logic := '0';
    signal reset_ok : std_logic := '0';

    signal sum : integer := 0;
    signal count : integer := 0;

    signal addr : std_logic_vector(3 downto 0) := (others => '0');
    signal data : std_logic_vector(7 downto 0);
    signal sum_vec : std_logic_vector(7 downto 0) := (others => '0');
    begin

    UUT: db_fsm PORT MAP(
    button => start,
    result => start_ok,
    clk => clk
    );

    UUT_Reset: db_fsm PORT MAP(
    button => reset,
    result => reset_ok,
    clk => clk
    );

    Inst_Rom_asyn: Rom_asyn PORT MAP(
    addr => addr,
    data => data
    );

    Inst_BaudRate: BaudRate PORT MAP(
    clk => clk,
    reset => reset_ok,
    baud => clk_slow
    );

    Inst_displayModule: displayModule PORT MAP(
    clk => clk,
    reset => reset_ok,
    val1 => sum_vec(7 downto 4),
    val2 => sum_vec(3 downto 0),
    C => C,
    display => display
    );

    process (clk_slow, start_ok, sum_vec)
    begin
    if (clk_slow'event and clk_slow = '1') then
    case (data) is
    when "00100001" =>
    if start_ok = '1' then
    addr <= "0001";
    end if;
    when "01011100" =>
    count <= to_integer(unsigned(din));
    sum <= 0;
    addr <= "0010";
    when "00011100" =>
    addr <= "0011";
    when "00100010" =>
    if count = 0 then
    addr <= "0000";
    else
    addr <= "0100";
    end if;
    when "01111100" =>
    sum <= sum + count;
    addr <= "0101";
    when "10011100" =>
    count <= count - 1;
    addr <= "0110";
    when "00101000" =>
    addr <= "0010";
    when others => addr <= addr;
    end case;
    end if;
    sum_vec <= std_logic_vector(to_unsigned(sum, sum_vec'length));
    end process;

    end Behavioral;



    Posted 1 year ago


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